One problem encountered in the testing of integrated circuits is that the lower cost testers that could ideally be used for testing lower pin count integrated circuits do not have a sufficient amount of scan test memory to provide the test quality levels desired. As the term is used herein, “integrated circuit” includes devices such as those formed on monolithic semiconducting substrates, such as those formed of group IV materials like silicon or germanium, or group III–V compounds like gallium arsenide, or mixtures of such materials. The term includes all types of devices formed, such as memory and logic, and all designs of such devices, such as MOS and bipolar. The term also comprehends applications such as flat panel displays, solar cells, and charge coupled devices.
While testers such as those described above can be upgraded with additional scan test memory, it is very expensive to do so. A full memory upgrade to a tester could range as high as about $400,000. However, this is currently the only existing solution to the problem. These memory upgrades provide a “transparent” solution to the problem, in that an existing tester only needs to be updated to recognize the additional memory capacity. From a test engineer's perspective, nothing changes with respect to the implementation of the associated scan test patterns.
For some testers, that additional capital expenditure is made for a fully depreciated tester, but in every case the upgrade results in increased test costs. For example, when a test subcontractor upgrades one of their testers with the additional scan memory, the test cost per second for that tester is effectively increased for all products tested on that machine, regardless of whether a given product makes use of the additional memory.
What is needed, therefore, is a system whereby problems such as those described above can be overcome, at least in part.